Embodiments of the present disclosure relate generally to semiconductor devices, and more particularly to semiconductor devices for controlling topologies of input data and semiconductor systems including the same.
As semiconductor devices become more highly integrated, a test time required to evaluate various characteristics of the semiconductor devices using a test equipment has been increased to guarantee the reliability thereof. Thus, the semiconductor devices (also referred to as semiconductor chips) are generally designed to include self test circuits embedded therein in order to reduce the test time and production cost.
A compressive parallel test utilizing the self test circuits may be performed by writing the same data in memory cells of a memory core and simultaneously reading out the data stored in the memory cells in order to verify that the data read out are identical to written data and in order to detect which memory cell has an error. The compressive parallel test may be performed using the minimum number of data pads (e.g., DQ pad) to remarkably reduce the test time of the semiconductor devices.
In general, the compressive parallel test may store the same data in all memory cells of the memory core. However, in some cases, different kinds of tests may be performed by storing data having different topologies in some memory cells (i.e., cell arrays) included in the memory core.